Encoding:

P32A

001000

rt

shift

ac

EXTR.W

00

111

001

111

111

P32A

001000

rt

shift

ac

EXTR_R.W

01

111

001

111

111

P32A

001000

rt

shift

ac

EXTR_RS.W

10

111

001

111

111

6

5

5

2

2

3

3

3

3

Format: 

EXTR[_RS].W

Extract Word Value With Right Shift From Accumulator to GPR

EXTR.W   rt, ac, shift

DSP

Extract Word Value With Right Shift From Accumulator to GPR

EXTR_R.W  rt, ac, shift

DSP

Extract Word Value With Right Shift From Accumulator to GPR

EXTR_RS.W rt, ac, shift

DSP

Extract Word Value With Right Shift From Accumulator to GPR

Purpose:

Extract Word Value With Right Shift From Accumulator to GPR

Extract a word value from a 64-bit accumulator to a GPR with right shift, and with optional rounding or rounding and saturation.

Description: 

rt = sat32(round(ac >> shift))

The value in accumulator ac is shifted right by shift bits with sign extension (arithmetic shift right). The 32 least-significant bits of the shifted value are then written to the destination register rs.

The rounding variant of the instruction adds a 1 at the most-significant discarded bit position. The 32 least-significant bits of the rounded result are then written to the destination register.

The rounding and saturating variant of the i nstruction adds a 1 at the most-significant discarded bit position. If the rounding operation results in an overflow, the shifted value is clamped to the maximum positive Q31 fractional value

(0x7FFFFFFF hexadecimal). The rounded and saturated result is then written to the destination register.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS32 architecture. After the execution of this instruction, ac remains unmodified.

For all variants of the instruction, including EXTR.W, bit 23 of the DSPControl register is set to 1 if either of the rounded or non-rounded calculation results in overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

EXTR.W
   ValidateAccessToDSPResources()
   temp64..0 = _shiftShortAccRightArithmetic( ac, shift )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF ) ) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]31..0 = temp32..1
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
   endif
EXTR_R.W
   ValidateAccessToDSPResources()
   temp64..0 = _shiftShortAccRightArithmetic( ac, shift )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]31..0 = temp32..1
EXTR_RS.W
   ValidateAccessToDSPResources()
   temp64..0 = _shiftShortAccRightArithmetic( ac, shift )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      if ( temp64 = 0 ) then
          temp32..1 = 0x7FFFFFFF
      else
          temp32..1 = 0x80000000
      endif
      DSPControlouflag:23 = 1
   endif
   GPR[rt]31..0 = temp32..1
function _shiftShortAccRightArithmetic( ac1..0, shift4..0 )
   if ( shift4..0 = 0 ) then
      temp64..0 = ( HI[ac]31..0 || LO[ac]31..0 || 0 )
   else
      temp64..0 = ( (HI[ac]31)shift || HI[ac]31..0 || LO[ac]31..shift-1 )
   endif
   return temp64..0
endfunction _shiftShortAccRightArithmetic

Exceptions:

Reserved Instruction, DSP Disabled